;	Hitachi SH Math Support
;	Copyright 1999 Metrowerks, Inc.

		.ENDIAN		LITTLE
		
		.EXPORT     __l_divu

		.SECTION    .text
		.ALIGN		4

;
;	unsigned int _l_divu(int I1, int I2)
;
;	Notes:
;	Runtime support routine.
;
__l_divu:


;	_divu32q	-	Quotient of 32 bit / 32bit (Unsigned)
;	
;	Input: 	R4	divident
;			R5	divisor
;	Output:	R0	quotient
;			T	error flag (T=1 : error)
;
;	Notes:
; 	Divides the divident (unsigned 32 bits) by the divisor (unsigned 32 bits)
;	and determines the quotient (unsigned 32 bits). Also indicates and error
;   (division by 0) in the T bit.
;

_divu32q:
		MOV		R5,R1
		MOV		R4,R0		; quotient
		
		TST		R1,R1		; divisor = 0 ?	
		BT		DIVU32Q1	; yes
		XOR		R2,R2		; R2 = H'00000000
		
		DIV0U				; divide as unsigned
		
		ROTCL	R0			; divide 1 step
		DIV1	R1,R2
		ROTCL	R0
		DIV1	R1,R2
		ROTCL	R0
		DIV1	R1,R2
		ROTCL	R0
		DIV1	R1,R2
		ROTCL	R0
		DIV1	R1,R2
		ROTCL	R0
		DIV1	R1,R2
		ROTCL	R0
		DIV1	R1,R2
		ROTCL	R0
		DIV1	R1,R2

		ROTCL	R0			
		DIV1	R1,R2
		ROTCL	R0
		DIV1	R1,R2
		ROTCL	R0
		DIV1	R1,R2
		ROTCL	R0
		DIV1	R1,R2
		ROTCL	R0
		DIV1	R1,R2
		ROTCL	R0
		DIV1	R1,R2
		ROTCL	R0
		DIV1	R1,R2
		ROTCL	R0
		DIV1	R1,R2

		ROTCL	R0			
		DIV1	R1,R2
		ROTCL	R0
		DIV1	R1,R2
		ROTCL	R0
		DIV1	R1,R2
		ROTCL	R0
		DIV1	R1,R2
		ROTCL	R0
		DIV1	R1,R2
		ROTCL	R0
		DIV1	R1,R2
		ROTCL	R0
		DIV1	R1,R2
		ROTCL	R0
		DIV1	R1,R2

		ROTCL	R0			
		DIV1	R1,R2
		ROTCL	R0
		DIV1	R1,R2
		ROTCL	R0
		DIV1	R1,R2
		ROTCL	R0
		DIV1	R1,R2
		ROTCL	R0
		DIV1	R1,R2
		ROTCL	R0
		DIV1	R1,R2
		ROTCL	R0
		DIV1	R1,R2
		ROTCL	R0
		DIV1	R1,R2

		ROTCL	R0

		RTS
		CLRT				; T bit = no error		
		
DIVU32Q1
		RTS
		SETT				; T bit = error
		
	  .END
